Lab Troubleshooting 💻

One of the purposes of the labs for this course is to teach you how to troubleshoot complex problems. This page has a few resources that can help you start that process.

FAQ

Where should I even start?
If you’re feeling lost, read the lab description again. The whole thing. A truly shocking number of students start working on the lab before reading the whole lab description. If you’re still feeling lost after reading the lab description, try some of these options:

Slow down. Take a deep breath. This problem has been solved before. A solution definitely exists.
Summarize the lab description. What are you trying to make? What does the finished product look like?
Break the assignment into smaller components. Solve the smallest problems first.
Use your resources. Between course materials, your peers, and the internet, the answer exists.
Ask your instructor a specific question.

If you’re still struggling to get started, my advice is to just do something. Write some Verilog. Simulate it. See what happens. We learn by doing, so you’re encouraged to experiment a bit.

Isn’t there a shortcut for this?
Yes. But that’s not what this course is about.

Did I break my FPGA?
Probably not, especially if you followed lab instructions and simulated your design first. My guess is that you still need to debug your design. If you think you broke your board, try to program a working (previously-tested) design onto it.

Common Error Messages

Some error messages are both common and opaque. This page should help you diagnose that.

Too many positional arguments

Error text: Too many positional arguments

This is caused by a glitch in Vivado. Fix it by navigating to Tools → Options → Synthesis. Then check the box for Disable incremental synthesis. This should resolve the issue.

Incorrect board/part selection

Error text: drc bivb-1 bank IO standard support: bank 34 has incompatible ios because the lvcmos33 io standard is not supported move the following ports or change their properties.

This is likely caused by incorrect board/part selection, either when creating the Vivado project or within the XDC file. Follow these steps:

Ensure the correct board is selected in Vivado by clicking the summation symbol $\sum$. The board should be Basys3, part xc7a35tcpg236-1.
Check for syntax errors in your constraints by opening the RTL analysis schematic to perform a constraint check.
Check the XDC file to ensure the correct LVCMOS declarations are correct. One or more LVCMOS33 declarations may have been changed to LVCMOS18. This can cause errors because an entire bank must be set to either 1.8 or 3.3 Volts. If a single pin in a bank is changed from 3.3 to 1.8 Volts, this causes errors in Vivado to avoid breaking the FPGA board. Your instructor can help with this, or you may wish to download a clean version of the XDC template and start from scratch.

Flash memory configuration

If an error indicates a problem with flash memory configuration, you likely need to update the chip specification in Vivado. In the Hardware section of Vivado, right-click the memory device and select Remove Configuration Memory Device from the dialogue that opens. Your instructor can help with this if needed.