Q12: Adders & Multipliers

Time Estimate15-30 minutes   Grade Impact0.5%   DueSep 21 @ 12pm  

Objective
Reinforce an understanding of NAND and NOR universal logic gates.

Additional Materials & Formats
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Free Response Questions

  1. Describe the difference between a half adder and a full adder.

  2. How can a subtractor be created using an adder? Explain the process of converting addition into subtraction.

  3. For building an n-bit arithmetic unit, compare your two favorite fast adders in terms of delay, complexity, and hardware cost.

Multiple Choice Questions

  1. The Sum output of a 1-bit full adder with inputs $A, B, C_{in}$ is:

    • $A + B + C_{in}$
    • $AB + AC_{in} + BC_{in}$
    • $A \oplus B \oplus C_{in}$
    • $(A+B)’(C_{in})$

  2. The Carry-out output $C_{out}$ of a 1-bit full adder is:

    • $A \oplus B \oplus C_{in}$
    • $AB + AC_{in} + BC_{in}$
    • $\lnot A \land \lnot B + C_{in}$
    • $\lnot (AB)$

  3. Which of the following statements is true about a 4-bit ripple-carry adder?

    • It has a constant delay regardless of the number of bits.
    • Each bit’s sum output is computed independently of the carry.
    • The carry-out from each bit must propagate to the next bit, causing delay.
    • It can only add unsigned numbers.

  4. To perform subtraction $A-B$ using an adder, a common method is to:

    • Invert $A+B$ directly
    • Use 1’s complement of $B$ only
    • Use 2’s complement: invert $B$ and add 1 at $C_{in}$
    • Swap $A$ and $B$ and ignore carry

  5. In a 4-bit ripple-carry adder, the main reason delay increases with bit-width is:

    • XOR gates cannot be cascaded
    • Each stage waits for carry from the previous stage
    • The sum output is always computed last by design rule
    • Borrow signals interfere with carry signals

  6. Which statement about simple multipliers is most accurate?

    • They avoid adders entirely
    • They generate partial products and then add them
    • They use only NOR gates with no carry logic
    • They are always faster than adders of similar width

  7. For a simple array multiplier, what dominates hardware growth as operand size increases?

    • Only inverter count
    • Number of partial products and adder cells
    • Number of clock cycles in combinational logic
    • Fan-out on a single output bit only
Backward L16: Multipliers H8: Adders & Multipliers Forward
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