H6: Signed & Unsigned

Time Estimate1-2 hours   Grade Impact1%   DueSep 14 @ 12pm  

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Notes

Show your work. You must show all steps of your work for full credit. While calculators can perform these calculations, demonstrating your process ensures understanding and mastery of the concepts.

Notation. To encourage flexibility between notations, the problems in this assignment use a variety of notations. We have discussed each style already; review the textbook or your notes if you need help.

Exercises

1. Write the decimal equivalent of these 12-bit numbers in 2’s complement:

   1. 0b110100101010
   2. 0b101001011010
   3. 0b111000111000
   4. 0b001100110011
   5. 0b111111111110

2. Make a table that lists the value of the following 12-bit Binary numbers interpreted with unsigned, sign-magnitude, 1’s complement, and 2’s complement numbers:

   1. 0b010101010101
   2. 0b111111000000
   3. 0b100000000000
   4. 0b111111111111
   5. 0b100000000001

3. Suppose you’re designing a processor for an embedded system with very limited hardware resources. The designer proposes using sign-magnitude because it’s “more intuitive.” Explain why this would be a poor choice, citing specific hardware complications that would arise during arithmetic operations.

4. Perform the following additions in 8-bit 1’s complement and show all work, including the end-around carry step. For each result, verify your answer by converting back to decimal and confirming correctness.

   1. 25 + (-10)
   2. (-30) + (-20)
   3. 45 + (-45)

5. Starting with the number 42 in 8-bit 2’s complement:

   1. Convert 42 to binary and then negate it to get -42.
   2. Now negate -42 to get back to 42.
   3. Negate the result from part B three more times, showing the binary after each negation.
   4. What do you observe? Explain why this behavior occurs and what it demonstrates about 2’s complement negation.

6. You are given a 4-bit adder and asked to design an add/sub unit. Draw a logic diagram showing how XOR gates would be placed to create an add/sub unit. Clearly label the A input, B input, Sub control signal, adder, and output. Explain what happens internally when Sub = 0 and when Sub = 1 in terms of the B operand transformation.

7. A junior engineer suggests replacing the XOR gates in an add/sub unit with AND gates instead. Explain why this would not work and describe what operation would actually be performed.

8. For each scenario, predict the output of an 8-bit add/sub unit without performing the full calculation. Explain your reasoning.

   1. A = 00110100, B = 00010010, Sub = 0. Will there be a carry out? Will overflow occur?
   2. A = 11110000, B = 00001111, Sub = 1. What operation is being performed in decimal? Estimate whether the result will be negative or positive.
   3. A = 10000000, B = 10000000, Sub = 0. What decimal values are A and B? Predict the output and whether overflow will occur.

9. Consider an add/sub unit that malfunctions: the XOR gates are working correctly, but the carry-in signal is always 0, even when Sub = 1. What operation would the unit perform when Sub = 1 is asserted? (Hint: think about what A + Inverted B + 0 equals.) Test your hypothesis with a concrete example: compute 10 - 3 with this broken unit. Show the binary steps and explain why the result is wrong.

10. Suppose you’re designing a 32-bit processor that uses 32-bit add/sub units for integer arithmetic. How many XOR gates would be required for the B input in a single add/sub unit? If a modern chip contains millions of transistors and each XOR gate requires approximately 4 transistors, calculate the approximate transistor count for XOR gates across 1,000 add/sub units. Comment on whether this is a significant fraction of chip area. Explain why, despite the simplicity of the XOR gate approach, modern processors might want to use more sophisticated adder designs in their add/sub units.

11. Bonus Challenge: Design a 2-bit Full Adder/Subtractor. Design a 2-bit full adder/subtractor that takes inputs A, B, Sub (control signal), and carry-in, and produces outputs S (sum/difference) and carry-out. Write the truth table for all possible input combinations. From the truth table, derive the Boolean expressions for S and carry-out. (Hint: S might be a complex expression; you may wish to use a Karnaugh map.) Explain how this 2-bit unit would be cascaded to build an 8-bit add/sub unit, and discuss how the Sub signal would propagate through the cascade. This problem is optional; no points will be lost if it is not completed. Up to 20 points of backup credit (which can be used to replace points lost in H5, H6, Q8, or Q9) are available for students who complete this problem. Students who complete this bonus challenge may use it as part of an assessment if desired.