Q3: Verilog & CAD

Time Estimate15-30 minutes   Grade Impact0.5%   DueSep 11 @ 12pm  

Objective
Reinforce an understanding of Verilog & CAD basics.

Additional Materials & Formats
Check Box for the most up-to-date versions of this lecture’s materials.

Free Response Questions

1. Why would someone use an HDL instead of schematic capture?

2. Briefly describe the difference between structural and behavioral circuit specification.

3. When would it be advantageous to use heirarchical design instead of explicitly designing an entire circuit?

Multiple Choice Questions

4. Which of the following is a valid Verilog module declaration?

   • Snippet A:

     module example;

   • Snippet B:

     module;

   • Snippet C:

     module example() 
         input A, B;
         output C;
     end module

   • Snippet D:

     module example();
     endmodule

5. What keyword(s) are used to declare ports? Select all that apply.

   • port
   • wire
   • input
   • output
   • reg
   • assign
   • parameter
   • param
   • always
   • initial
   • generate

6. Which of the following is an example of continuous assignment?

   • Snippet A:

     and(C, A, B);

   • Snippet B:

     always @(*)
     begin
         C = A & B;
     end

   • Snippet C:

     initial begin
         A = 0;
     end

   • Snippet D:

     assign Y = A | B;

7. Which of the following correctly describes the sensitivity list of an always block in Verilog?

   • It specifies the variables that are updated inside the always block.
   • It determines the output conditions of the always block.
   • It lists the signals that trigger the execution of the always block.
   • It must be used to declare a clock for the always block.

8. Which of the following statements best describes the difference between using Verilog primitives (e.g., and, or, not) and more advanced constructs (e.g., always blocks, assign statements)?

   • Primitives are used exclusively for simulation, while advanced constructs are used for synthesis.
   • Advanced constructs allow for more complex behavior and are better suited for behavioral modeling.
   • Primitives are faster to simulate and synthesize but cannot describe full logic circuits.
   • There is no meaningful difference.

9. Which of the following statements best describes the difference between wire and reg in Verilog?

   • wire is used for storing values, while reg is used for connecting modules.
   • reg is used for storing values, while wire is used for connecting modules.
   • wire is used for declaring inputs and outputs, while reg is used for internal signals.
   • reg is used for declaring inputs and outputs, while wire is used for internal signals.
   • wire and reg are interchangeable in all contexts.

10. Why should an engineer simulate circuit designs before implementing them in hardware?

    • To ensure the design meets functional requirements and behaves as expected.
    • To save time and resources by identifying errors early in the design process.
    • To verify that the design is optimized for performance and resource usage.
    • To avoid catastrophic consequences of bugs in real-world hardware.
    • All of the above.