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Q15: Latches & Flip-Flops#

Time Estimate15-30 minutes   Grade Impact0.5%   DueSep 21 @ 12pm  

Objective
Reinforce an understanding of NAND and NOR universal logic gates.

Free Response Questions#

  1. What is the difference between a latch and a flip-flop in terms of their input signals and output behavior?

  2. Explain how a D flip-flop can be constructed using two D latches in a master-slave configuration.

  3. Explain the difference between a gated SR latch and a gated D latch in terms of input signals and output behavior.

Multiple Choice Questions#

  1. Which of the following statements about flip-flops is true?

    • A flip-flop can only have one input.
    • A flip-flop can have multiple outputs.
    • A flip-flop is a bistable device that changes state on a clock edge.
    • A flip-flop requires a register to function.

  2. Which of the following statements about latches is true?

    • A latch can only have one input.
    • A latch can have multiple outputs.
    • A latch is a bistable device that changes state on a clock edge.
    • A latch is level-sensitive and can change state when the enable signal is active.

  3. Which of the following is a sub-component of a JK flip-flop?

    • D latch
    • T flip-flop
    • Gated SR latch
    • 4-to-1 multiplexer

  4. Which of the following is a sub-component of a D flip-flop?

    • JK flip-flop
    • T flip-flop
    • Gated D latch
    • 8-to-1 multiplexer

  5. What does a T flip-flop do when its T input is high and a clock edge occurs?

    • It toggles its output state.
    • It resets its output to 0.
    • It sets its output to 1.
    • It maintains its current output state.

  6. What is the purpose of the clear and preset inputs in a flip-flop?

    • They control the clock signal.
    • They force the output to a specific state regardless of other inputs.
    • They toggle the output state on each clock edge.
    • They enable or disable the flip-flop’s operation.

  7. Why are the outputs of a gated SR latch considered to be in an indeterminate state when both S and R inputs are high?

    • Because the latch is level-sensitive and can change state when the enable signal is active.
    • Because the latch is bistable and can only hold one state at a time.
    • Because the latch is edge-triggered and can only change state on a clock edge.
    • Because the latch is asynchronous and can change state at any time.
Backward H11: Flip-Flops L23: Registers Forward
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