Full Course Table of Contents#

M0: Introduction#

• Lectures
  • L0: Introduction
• Assigned Reading
  • Start Here
  • Course Policies
  • Official Syllabus (available on Canvas)
  • 1.1–1.3 (Introductory Materials)
• Homework
  • H0: ECE Format
• Quizzes
  • Q0: Baseline Quiz
• Labs
  • Lab0: Gitting Started

M1: Digital Systems#

• Lectures
  • L1: Number Systems
  • L2: Logic Circuits
  • L3: Verilog & CAD
  • L4: Clocks
• Required Textbook Reading
  • 1.5 (Digital Representation of Information)
  • 3.1 (Positional Number Representation)
  • 3.7 (Other Number Representations)
  • 2.1 (Variables and Functions)
  • 2.2 (Inversion)
  • 2.3 (Truth Tables)
  • 2.4 (Logic Gates & Networks)
  • 2.9 (Introduction to CAD Tools)
  • 2.10 (Introduction to Verilog)
  • Skim A.1–A.12 (Verilog Reference)
• Optional Supplemental Materials
  • Khan Acadamy Videos: Alternate Number Bases (8 useful videos in the sidebar)
  • Boolean Logic & Logic Gates - Crash Course Computer Science
  • Introduction to Verilog - ChipVerify
  • An Introduction to Verilog - CompArchIllinois on YouTube
  • Introduction to Verilog - Carleton University
• Homework
  • H1: Number Systems
  • H2: Logic Circuits
• Quizzes
  • Q1: Number Systems
  • Q2: Logic Circuits
  • Q3: Verilog & CAD
• Labs
  • Lab1: CAD Workflow
  • Lab2: Verilog Exploration

M2: Boolean Algebra#

• Lectures
  • L5: Axioms
  • L6: Equivalence
  • L7: Theorems A
  • L8: Theorems B
  • L9: PoS and SoP
  • L10: Minimization
• Required Textbook Reading
  • 2.3 (Truth Tables)
  • 2.4 (Logic Gates & Networks)
  • 2.5 (Boolean Algebra)
  • 2.6.1 (Sum-of-Products and Product-of-Sums Forms)
  • 2.11 (Minimization and Karnaugh Maps)
  • 2.12 (Strategy for Minimization)
  • 2.13 (Minimization of Product-of-Sums Forms)
  • 2.14 (Incompletely Specified Functions)
• Optional Supplemental Materials
  • Boolean algebra (Wikipedia) – deep dive into the history and laws of Boolean algebra
  • The Mathematics of Boolean Algebra (Stanford Encyclopedia of Philosophy) – philosophical look at Boolean algebra, a perspective you don’t always get in computing courses
  • Boolean Algebra in 13 Minutes (TrevTutor on YouTube) – quick but helpful overview
  • Neso Academy videos:
    • Sum of Products (SOP) Form - Part 1
    • Sum of Products (SOP) Form - Part 2
    • Product of Sums (POS) - Part 1
    • Product of Sums (POS) - Part 2
    • SOP and POS Form Examples
  • Boolean Function Representation: SOP and POS Form | Minterms and Maxterms Explained – All About Electronics on YouTube
  • Introduction to Karnaugh Maps – The Organic Chemistry Tutor on YouTube
  • Karnaugh map – Wikipedia (for a deep dive)
• Homework
  • H3: Equivalence
  • H4: Boolean Algebra
  • H5: Minimization
• Quizzes
  • Q4: Equivalence
  • Q5: Theorems
  • Q6: PoS and SoP
  • Q7: Minimization
• Labs
  • Lab3: Combinational Circuits
  • Lab4: Seven Segment Display

M3: Arithmetic#

• Lectures
  • L11: Unsigned Arithmetic
  • L12: Signed Arithmetic
  • L13: Universal Gates
  • L14: Circuit Synthesis
  • L15: Adders
  • L16: Multipliers
  • L17: Verilog Arithmetic
• Assigned Reading
  • 3.2 (Unsigned Numbers)
  • 3.3 (Signed Numbers)
  • 2.6–2.7 (Universal Gates)
  • 3.4 (Fast Adders)
  • 3.5 (Design of Arithmetic Circuits Using CAD Tools)
  • 3.6 (Multiplication)
• Homework
  • H6: Signed & Unsigned
  • H7: Universal Gates
  • H8: Adders & Multipliers
• Quizzes
  • Q8: Unsigned Arithmetic
  • Q9: Signed Arithmetic
  • Q10: Universal Gates
  • Q11: Circuit Synthesis
  • Q12: Adders & Multipliers
• Labs
  • Lab5: Signed & Unsigned
  • Lab6: Arithmetic Circuits

Midterm Assessment#

Covers M1–M3. See the Assessment Ideas for more information and inspiration.

M4: Building Blocks#

• Lectures
  • L18: Multiplexers
  • L19: Decoders & Encoders
  • L20: Comparators
  • L21: Latches
  • L22: Flip Flops
  • L23: Registers
  • L24: Counters
  • L25: Modular Design
• Assigned Reading
  • 4.1 (Multiplexers)
  • 4.2–4.4 (Decoders & Encoders)
  • 4.5 (Comparison Circuits)
  • 5.1–5.3 (Latches)
  • 5.4–5.7 (Flip Flops)
  • 5.8 (Registers)
  • 5.9–5.11 (Counters)
  • 5.12–5.15 (Modular Design)
• Homework
  • H9: Multiplexers, Decoders & Encoders
  • H10: Latches
  • H11: Flip-Flops
  • H12: Registers & Counters
• Quizzes
  • Q13: Multiplexers
  • Q14: Decoders & Encoders
  • Q15: Latches & Flip-Flops
  • Q16: Registers & Counters
• Labs
  • Lab7: Building with Blocks
  • Lab8: Decoding & Encoding

M5: State Machines#

• Lectures
  • L26: Sequential Circuits
  • L27: State Machines A
  • L28: State Machines B
  • L29: State Minimization
  • L30: Verilog State Machines
• Assigned Reading
  • 6.1–6.3 (State Machines)
  • 6.4 (Design of FSMs using CAD Tools)
  • 6.5–6.8 (Case Studies)
  • 6.10-6.11 (State Machine Models)
• Homework
  • H13: State Machines
  • H14: Verilog State Machines
• Quizzes
  • Q17: Sequential Circuits
  • Q18: State Machines
  • Q19: State Machines
• Labs
  • Lab10: State Machines
  • Lab11: Debouncers

M6: Advanced Concepts#

• Lectures
  • L31: Advanced Circuits
  • L32: FPGAs in the Wild
  • L33: Formal Verification
• Extra Credit
  • IDEA Survey
• No reading, homework, quizzes, or labs.

Final Assessment#

Cumulative, prioritizing M4–M6. See the Assessment Ideas for more information and inspiration.