L4: Clocks

Circuits should run on time.

Objective
Introduce clocks as elements of digital design.

Additional Materials & Formats
Check Box for the most up-to-date versions of this lecture’s materials.

Before the Lecture

No assigned reading! 🎉

Clocks in Digital Design

Clocks are fundamental to synchronous digital systems, providing the timing reference that coordinates the operation of all sequential elements in a design. A clock signal is a periodic waveform, typically a square wave, that alternates between high and low states at a fixed frequency. This signal ensures that data is processed in a predictable and orderly manner.

Clock Characteristics

Frequency: The number of clock cycles per second, measured in hertz (Hz). It determines the speed at which a circuit operates.
Period: The duration of one complete clock cycle, which is the reciprocal of the frequency. $$ T = \frac{1}{f} $$
Duty Cycle: The percentage of the clock period during which the signal is high. A 50% duty cycle is common, where the clock is high for half the period and low for the other half.
Phase: The relative timing of the clock signal with respect to another signal or clock. Phase differences are critical in multi-clock systems.
Jitter: The variation in the timing of clock edges, which can affect the reliability of high-speed designs.

Clock Generation

In Verilog, clocks are often generated in testbenches using an initial block with a forever loop or a repeat loop. For example:

reg clk;

initial begin
     clk = 0; // Initialize clock
     forever #5 clk = ~clk; // Toggle clock every 5 time units
end

This code creates a clock signal with a period of 10 time units and a 50% duty cycle, shown below:

Clock Domains

In complex systems, multiple clock signals with different frequencies or phases may be used. These are referred to as clock domains. Communication between clock domains requires careful design to avoid issues such as metastability. In this course, your designs should always have only one clock.

Clock Gating

Clock gating is a technique used to reduce power consumption by disabling the clock signal to parts of the circuit that are not in use. This is achieved by adding a control signal to the clock path:

module clock_gating (
     input clk,
     input enable,
     output gated_clk
);

     assign gated_clk = clk & enable;

endmodule

Clock in Sequential Circuits

Sequential circuits (which we will cover in the second half of this course) rely on the clock signal to determine when to capture and propagate data. The clock edge (rising or falling) triggers these operations. For example:

always @(posedge clk) begin
     q <= d; // Capture data on the rising edge of the clock
end

Clocks in Testbenches

Clocks play a critical role in driving testbench simulation. A typical testbench includes a clock generator to provide the timing reference for the design under test (DUT). Here’s an example of a simple clocked testbench from Lab2:

module testbench(
);
    reg in1, in2, clk;
    wire out;

    myandgate DUT (.A(in1), .B(in2), .F(out));

    initial begin
        in1 = 0; in2 = 0; clk = 0;
        forever #10 clk = ~clk;
    end
endmodule

In this example:

The clock toggles every 10 time units, creating a clock period of 20 time units.
The forever loop ensures the clock runs continuously throughout the simulation.

Testbenches often include multiple clocks for designs with multiple clock domains. Care must be taken to ensure proper synchronization between these clocks.

Clock Dividers

Clock dividers reduce a fast clock to a slower one by counting input edges and toggling an output when a threshold is reached. Common uses include human-visible blink rates and generating sampling clocks.

Practice
As a class, let’s implement a human-based clock divider.